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iomux.h File Reference


Detailed Description

I/O Muxing control definitions and functions.

Definition in file iomux.h.

#include <linux/types.h>
#include <mach/gpio.h>
#include "mx25_pins.h"

Go to the source code of this file.

Classes

struct  mxc_iomux_pin_cfg

Typedefs

typedef enum iomux_gp_func iomux_gp_func_t
typedef enum iomux_input_config iomux_input_cfg_t
typedef enum iomux_input_select iomux_input_select_t
typedef enum iomux_pad_config iomux_pad_config_t
typedef enum iomux_pin_config iomux_pin_cfg_t
typedef unsigned int iomux_pin_name_t

Enumerations

enum  iomux_gp_func {
  MUX_SDCTL_CSD0_SEL = 0x1 << 0, MUX_SDCTL_CSD1_SEL = 0x1 << 1, MUX_PGP_FIRI = 0x1 << 0, MUX_DDR_MODE = 0x1 << 1,
  MUX_PGP_CSPI_BB = 0x1 << 2, MUX_PGP_ATA_1 = 0x1 << 3, MUX_PGP_ATA_2 = 0x1 << 4, MUX_PGP_ATA_3 = 0x1 << 5,
  MUX_PGP_ATA_4 = 0x1 << 6, MUX_PGP_ATA_5 = 0x1 << 7, MUX_PGP_ATA_6 = 0x1 << 8, MUX_PGP_ATA_7 = 0x1 << 9,
  MUX_PGP_ATA_8 = 0x1 << 10, MUX_PGP_UH2 = 0x1 << 11, MUX_SDCTL_CSD0_SEL = 0x1 << 12, MUX_SDCTL_CSD1_SEL = 0x1 << 13,
  MUX_CSPI1_UART3 = 0x1 << 14, MUX_EXTDMAREQ2_MBX_SEL = 0x1 << 15, MUX_TAMPER_DETECT_EN = 0x1 << 16, MUX_PGP_USB_4WIRE = 0x1 << 17,
  MUX_PGB_USB_COMMON = 0x1 << 18, MUX_SDHC_MEMSTICK1 = 0x1 << 19, MUX_SDHC_MEMSTICK2 = 0x1 << 20, MUX_PGP_SPLL_BYP = 0x1 << 21,
  MUX_PGP_UPLL_BYP = 0x1 << 22, MUX_PGP_MSHC1_CLK_SEL = 0x1 << 23, MUX_PGP_MSHC2_CLK_SEL = 0x1 << 24, MUX_CSPI3_UART5_SEL = 0x1 << 25,
  MUX_PGP_ATA_9 = 0x1 << 26, MUX_PGP_USB_SUSPEND = 0x1 << 27, MUX_PGP_USB_OTG_LOOPBACK = 0x1 << 28, MUX_PGP_USB_HS1_LOOPBACK = 0x1 << 29,
  MUX_PGP_USB_HS2_LOOPBACK = 0x1 << 30, MUX_CLKO_DDR_MODE = 0x1 << 31, MUX_SDCTL_CSD0_SEL = 0x1 << 0, MUX_SDCTL_CSD1_SEL = 0x1 << 1,
  MUX_TAMPER_DETECT_EN = 0x1 << 2, MUX_IPD_ESDHC_DREQ_B = 0x0 << 0, MUX_XDRQ = 0x1 << 0, MUX_EMI_DMA_ACCESS_1 = 0x0 << 4,
  MUX_KEY_COL2 = 0x1 << 4, MUX_TAMPER_DETECT_EN = 0x1 << 8, MUX_IPUv3D_TVE = 0x0 << 12, MUX_IPUv3D_CAMP = 0x1 << 12
}
enum  iomux_input_config {
  INPUT_CTL_PATH0 = 0x0, INPUT_CTL_PATH1, INPUT_CTL_PATH2, INPUT_CTL_PATH3,
  INPUT_CTL_PATH4, INPUT_CTL_PATH5, INPUT_CTL_PATH6, INPUT_CTL_PATH7,
  INPUTCONFIG_NONE = 0, INPUTCONFIG_GPIO = 1 << 0, INPUTCONFIG_FUNC = 1 << 1, INPUTCONFIG_ALT1 = 1 << 2,
  INPUTCONFIG_ALT2 = 1 << 3, INPUT_CTL_PATH0 = 0x0, INPUT_CTL_PATH1, INPUT_CTL_PATH2,
  INPUT_CTL_PATH3, INPUT_CTL_PATH4, INPUT_CTL_PATH5, INPUT_CTL_PATH6,
  INPUT_CTL_PATH7, INPUT_CTL_PATH0 = 0x0, INPUT_CTL_PATH1, INPUT_CTL_PATH2,
  INPUT_CTL_PATH3, INPUT_CTL_PATH4, INPUT_CTL_PATH5, INPUT_CTL_PATH6,
  INPUT_CTL_PATH7, INPUT_CTL_PATH0 = 0x0, INPUT_CTL_PATH1, INPUT_CTL_PATH2,
  INPUT_CTL_PATH3, INPUT_CTL_PATH4, INPUT_CTL_PATH5, INPUT_CTL_PATH6,
  INPUT_CTL_PATH7
}
enum  iomux_input_select {
  MUX_IN_AUDMUX_P4_INPUT_DA_AMX = 0, MUX_IN_AUDMUX_P4_INPUT_DB_AMX, MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX, MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX,
  MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX, MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX, MUX_IN_AUDMUX_P7_INPUT_DA_AMX, MUX_IN_AUDMUX_P7_INPUT_TXFS_AMX,
  MUX_IN_CAN1_IPP_IND_CANRX, MUX_IN_CAN2_IPP_IND_CANRX, MUX_IN_CSI_IPP_CSI_D_0, MUX_IN_CSI_IPP_CSI_D_1,
  MUX_IN_CSPI1_IPP_IND_SS3_B, MUX_IN_CSPI2_IPP_CSPI_CLK_IN, MUX_IN_CSPI2_IPP_IND_DATAREADY_B, MUX_IN_CSPI2_IPP_IND_MISO,
  MUX_IN_CSPI2_IPP_IND_MOSI, MUX_IN_CSPI2_IPP_IND_SS0_B, MUX_IN_CSPI2_IPP_IND_SS1_B, MUX_IN_CSPI3_IPP_CSPI_CLK_IN,
  MUX_IN_CSPI3_IPP_IND_DATAREADY_B, MUX_IN_CSPI3_IPP_IND_MISO, MUX_IN_CSPI3_IPP_IND_MOSI, MUX_IN_CSPI3_IPP_IND_SS0_B,
  MUX_IN_CSPI3_IPP_IND_SS1_B, MUX_IN_CSPI3_IPP_IND_SS2_B, MUX_IN_CSPI3_IPP_IND_SS3_B, MUX_IN_ESDHC1_IPP_DAT4_IN,
  MUX_IN_ESDHC1_IPP_DAT5_IN, MUX_IN_ESDHC1_IPP_DAT6_IN, MUX_IN_ESDHC1_IPP_DAT7_IN, MUX_IN_ESDHC2_IPP_CARD_CLK_IN,
  MUX_IN_ESDHC2_IPP_CMD_IN, MUX_IN_ESDHC2_IPP_DAT0_IN, MUX_IN_ESDHC2_IPP_DAT1_IN, MUX_IN_ESDHC2_IPP_DAT2_IN,
  MUX_IN_ESDHC2_IPP_DAT3_IN, MUX_IN_ESDHC2_IPP_DAT4_IN, MUX_IN_ESDHC2_IPP_DAT5_IN, MUX_IN_ESDHC2_IPP_DAT6_IN,
  MUX_IN_ESDHC2_IPP_DAT7_IN, MUX_IN_FEC_FEC_COL, MUX_IN_FEC_FEC_CRS, MUX_IN_FEC_FEC_RDATA_2,
  MUX_IN_FEC_FEC_RDATA_3, MUX_IN_FEC_FEC_RX_CLK, MUX_IN_FEC_FEC_RX_ER, MUX_IN_I2C2_IPP_SCL_IN,
  MUX_IN_I2C2_IPP_SDA_IN, MUX_IN_I2C3_IPP_SCL_IN, MUX_IN_I2C3_IPP_SDA_IN, MUX_IN_KPP_IPP_IND_COL_4,
  MUX_IN_KPP_IPP_IND_COL_5, MUX_IN_KPP_IPP_IND_COL_6, MUX_IN_KPP_IPP_IND_COL_7, MUX_IN_KPP_IPP_IND_ROW_4,
  MUX_IN_KPP_IPP_IND_ROW_5, MUX_IN_KPP_IPP_IND_ROW_6, MUX_IN_KPP_IPP_IND_ROW_7, MUX_IN_SIM1_PIN_SIM_RCVD1_IN,
  MUX_IN_SIM1_PIN_SIM_SIMPD1, MUX_IN_SIM1_SIM_RCVD1_IO, MUX_IN_SIM2_PIN_SIM_RCVD1_IN, MUX_IN_SIM2_PIN_SIM_SIMPD1,
  MUX_IN_SIM2_SIM_RCVD1_IO, MUX_IN_UART3_IPP_UART_RTS_B, MUX_IN_UART3_IPP_UART_RXD_MUX, MUX_IN_UART4_IPP_UART_RTS_B,
  MUX_IN_UART4_IPP_UART_RXD_MUX, MUX_IN_UART5_IPP_UART_RTS_B, MUX_IN_UART5_IPP_UART_RXD_MUX, MUX_IN_USB_TOP_IPP_IND_OTG_USB_OC,
  MUX_IN_USB_TOP_IPP_IND_UH2_USB_OC, MUX_IN_AMX_P5_RXCLK = 0, MUX_IN_AMX_P5_RXFS, MUX_IN_AMX_P6_DA,
  MUX_IN_AMX_P6_DB, MUX_IN_AMX_P6_RXCLK, MUX_IN_AMX_P6_RXFS, MUX_IN_AMX_P6_TXCLK,
  MUX_IN_AMX_P6_TXFS, MUX_IN_CAN1_CANRX, MUX_IN_CAN2_CANRX, MUX_IN_CCM_32K_MUXED,
  MUX_IN_CCM_PMIC_RDY, MUX_IN_CSPI1_SS2_B, MUX_IN_CSPI1_SS3_B, MUX_IN_CSPI2_CLK_IN,
  MUX_IN_CSPI2_DATAREADY_B, MUX_IN_CSPI2_MISO, MUX_IN_CSPI2_MOSI, MUX_IN_CSPI2_SS0_B,
  MUX_IN_CSPI2_SS1_B, MUX_IN_CSPI2_SS2_B, MUX_IN_CSPI2_SS3_B, MUX_IN_EMI_WEIM_DTACK_B,
  MUX_IN_ESDHC1_DAT4_IN, MUX_IN_ESDHC1_DAT5_IN, MUX_IN_ESDHC1_DAT6_IN, MUX_IN_ESDHC1_DAT7_IN,
  MUX_IN_ESDHC3_CARD_CLK_IN, MUX_IN_ESDHC3_CMD_IN, MUX_IN_ESDHC3_DAT0, MUX_IN_ESDHC3_DAT1,
  MUX_IN_ESDHC3_DAT2, MUX_IN_ESDHC3_DAT3, MUX_IN_GPIO1_IN_0, MUX_IN_GPIO1_IN_10,
  MUX_IN_GPIO1_IN_11, MUX_IN_GPIO1_IN_1, MUX_IN_GPIO1_IN_20, MUX_IN_GPIO1_IN_21,
  MUX_IN_GPIO1_IN_22, MUX_IN_GPIO1_IN_2, MUX_IN_GPIO1_IN_3, MUX_IN_GPIO1_IN_4,
  MUX_IN_GPIO1_IN_5, MUX_IN_GPIO1_IN_6, MUX_IN_GPIO1_IN_7, MUX_IN_GPIO1_IN_8,
  MUX_IN_GPIO1_IN_9, MUX_IN_GPIO2_IN_0, MUX_IN_GPIO2_IN_10, MUX_IN_GPIO2_IN_11,
  MUX_IN_GPIO2_IN_12, MUX_IN_GPIO2_IN_13, MUX_IN_GPIO2_IN_14, MUX_IN_GPIO2_IN_15,
  MUX_IN_GPIO2_IN_16, MUX_IN_GPIO2_IN_17, MUX_IN_GPIO2_IN_18, MUX_IN_GPIO2_IN_19,
  MUX_IN_GPIO2_IN_1, MUX_IN_GPIO2_IN_20, MUX_IN_GPIO2_IN_21, MUX_IN_GPIO2_IN_22,
  MUX_IN_GPIO2_IN_23, MUX_IN_GPIO2_IN_24, MUX_IN_GPIO2_IN_25, MUX_IN_GPIO2_IN_26,
  MUX_IN_GPIO2_IN_27, MUX_IN_GPIO2_IN_28, MUX_IN_GPIO2_IN_29, MUX_IN_GPIO2_IN_2,
  MUX_IN_GPIO2_IN_30, MUX_IN_GPIO2_IN_31, MUX_IN_GPIO2_IN_3, MUX_IN_GPIO2_IN_4,
  MUX_IN_GPIO2_IN_5, MUX_IN_GPIO2_IN_6, MUX_IN_GPIO2_IN_7, MUX_IN_GPIO2_IN_8,
  MUX_IN_GPIO2_IN_9, MUX_IN_GPIO3_IN_0, MUX_IN_GPIO3_IN_10, MUX_IN_GPIO3_IN_11,
  MUX_IN_GPIO3_IN_12, MUX_IN_GPIO3_IN_13, MUX_IN_GPIO3_IN_14, MUX_IN_GPIO3_IN_15,
  MUX_IN_GPIO3_IN_4, MUX_IN_GPIO3_IN_5, MUX_IN_GPIO3_IN_6, MUX_IN_GPIO3_IN_7,
  MUX_IN_GPIO3_IN_8, MUX_IN_GPIO3_IN_9, MUX_IN_I2C3_SCL_IN, MUX_IN_I2C3_SDA_IN,
  MUX_IN_IPU_DISPB_D0_VSYNC, MUX_IN_IPU_DISPB_D12_VSYNC, MUX_IN_IPU_DISPB_SD_D, MUX_IN_IPU_SENSB_DATA_0,
  MUX_IN_IPU_SENSB_DATA_1, MUX_IN_IPU_SENSB_DATA_2, MUX_IN_IPU_SENSB_DATA_3, MUX_IN_IPU_SENSB_DATA_4,
  MUX_IN_IPU_SENSB_DATA_5, MUX_IN_IPU_SENSB_DATA_6, MUX_IN_IPU_SENSB_DATA_7, MUX_IN_KPP_COL_0,
  MUX_IN_KPP_COL_1, MUX_IN_KPP_COL_2, MUX_IN_KPP_COL_3, MUX_IN_KPP_COL_4,
  MUX_IN_KPP_COL_5, MUX_IN_KPP_COL_6, MUX_IN_KPP_COL_7, MUX_IN_KPP_ROW_0,
  MUX_IN_KPP_ROW_1, MUX_IN_KPP_ROW_2, MUX_IN_KPP_ROW_3, MUX_IN_KPP_ROW_4,
  MUX_IN_KPP_ROW_5, MUX_IN_KPP_ROW_6, MUX_IN_KPP_ROW_7, MUX_IN_OWIRE_BATTERY_LINE,
  MUX_IN_SPDIF_HCKT_CLK2, MUX_IN_SPDIF_SPDIF_IN1, MUX_IN_UART3_UART_RTS_B, MUX_IN_UART3_UART_RXD_MUX,
  MUX_IN_USB_OTG_DATA_0, MUX_IN_USB_OTG_DATA_1, MUX_IN_USB_OTG_DATA_2, MUX_IN_USB_OTG_DATA_3,
  MUX_IN_USB_OTG_DATA_4, MUX_IN_USB_OTG_DATA_5, MUX_IN_USB_OTG_DATA_6, MUX_IN_USB_OTG_DATA_7,
  MUX_IN_USB_OTG_DIR, MUX_IN_USB_OTG_NXT, MUX_IN_USB_UH2_DATA_0, MUX_IN_USB_UH2_DATA_1,
  MUX_IN_USB_UH2_DATA_2, MUX_IN_USB_UH2_DATA_3, MUX_IN_USB_UH2_DATA_4, MUX_IN_USB_UH2_DATA_5,
  MUX_IN_USB_UH2_DATA_6, MUX_IN_USB_UH2_DATA_7, MUX_IN_USB_UH2_DIR, MUX_IN_USB_UH2_NXT,
  MUX_IN_USB_UH2_USB_OC, MUX_IN_CCM_PLL1_BYPASS_CLK = 0, MUX_IN_CCM_PLL2_BYPASS_CLK, MUX_IN_CCM_PLL3_BYPASS_CLK,
  MUX_IN_CSPI3_CSPI_CLK, MUX_IN_CSPI3_MISO, MUX_IN_CSPI3_MOSI, MUX_IN_EMI_READ_MADDR_DATA_0,
  MUX_IN_EMI_READ_MADDR_DATA_10, MUX_IN_EMI_READ_MADDR_DATA_11, MUX_IN_EMI_READ_MADDR_DATA_12, MUX_IN_EMI_READ_MADDR_DATA_13,
  MUX_IN_EMI_READ_MADDR_DATA_14, MUX_IN_EMI_READ_MADDR_DATA_15, MUX_IN_EMI_READ_MADDR_DATA_1, MUX_IN_EMI_READ_MADDR_DATA_2,
  MUX_IN_EMI_READ_MADDR_DATA_3, MUX_IN_EMI_READ_MADDR_DATA_4, MUX_IN_EMI_READ_MADDR_DATA_5, MUX_IN_EMI_READ_MADDR_DATA_6,
  MUX_IN_EMI_READ_MADDR_DATA_7, MUX_IN_EMI_READ_MADDR_DATA_8, MUX_IN_EMI_READ_MADDR_DATA_9, MUX_IN_EMI_NFC_READ_DATA_IN_0,
  MUX_IN_EMI_NFC_READ_DATA_IN_10, MUX_IN_EMI_NFC_READ_DATA_IN_11, MUX_IN_EMI_NFC_READ_DATA_IN_12, MUX_IN_EMI_NFC_READ_DATA_IN_13,
  MUX_IN_EMI_NFC_READ_DATA_IN_14, MUX_IN_EMI_NFC_READ_DATA_IN_15, MUX_IN_EMI_NFC_READ_DATA_IN_1, MUX_IN_EMI_NFC_READ_DATA_IN_2,
  MUX_IN_EMI_NFC_READ_DATA_IN_3, MUX_IN_EMI_NFC_READ_DATA_IN_4, MUX_IN_EMI_NFC_READ_DATA_IN_5, MUX_IN_EMI_NFC_READ_DATA_IN_6,
  MUX_IN_EMI_NFC_READ_DATA_IN_7, MUX_IN_EMI_NFC_READ_DATA_IN_8, MUX_IN_EMI_NFC_READ_DATA_IN_9, MUX_IN_FEC_FEC_COL,
  MUX_IN_FEC_FEC_CRS, MUX_IN_FEC_FEC_MDI, MUX_IN_FEC_FEC_RDATA_0, MUX_IN_FEC_FEC_RX_CLK,
  MUX_IN_FEC_FEC_RX_DV, MUX_IN_FEC_FEC_RX_ER, MUX_IN_FEC_FEC_TX_CLK, MUX_IN_I2C1_SCL,
  MUX_IN_I2C1_SDA, MUX_IN_I2C2_SCL, MUX_IN_I2C2_SDA, MUX_IN_I2C3_SCL,
  MUX_IN_I2C3_SDA, MUX_IN_IPU_DI_0_IND_DISPB_D0_VSYNC, MUX_IN__IPU_DI_0_IND_DISPB_SD_D, MUX_IN_KPP_ROW_0,
  MUX_IN_KPP_ROW_1, MUX_IN_KPP_ROW_2, MUX_IN_KPP_ROW_3, MUX_IN_KPP_ROW_4,
  MUX_IN_KPP_ROW_5, MUX_IN_KPP_ROW_6, MUX_IN_KPP_ROW_7, MUX_IN_UART1_UART_RTS_B,
  MUX_IN_UART1_UART_RXD_MUX, MUX_IN_UART2_UART_RTS_B, MUX_IN_UART2_UART_RXD_MUX, MUX_IN_UART3_UART_RTS_B,
  MUX_IN_UART3_UART_RXD_MUX, MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
  MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
  MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
  MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
  MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
  MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
  MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
  MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
  MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, MUX_IN_FEC_FEC_COL_SELECT_INPUT,
  MUX_IN_FEC_FEC_CRS_SELECT_INPUT, MUX_IN_FEC_FEC_MDI_SELECT_INPUT, MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
  MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
  MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
  MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
  MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
  MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
  MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
  MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
  MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
  MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
  MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
  MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
  MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
  MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, MUX_INPUT_NUM_MUX
}
enum  iomux_pad_config {
  PAD_CTL_DRV_3_3V = 0x0 << 13, PAD_CTL_DRV_1_8V = 0x1 << 13, PAD_CTL_HYS_CMOS = 0x0 << 8, PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
  PAD_CTL_PKE_NONE = 0x0 << 7, PAD_CTL_PKE_ENABLE = 0x1 << 7, PAD_CTL_PUE_KEEPER = 0x0 << 6, PAD_CTL_PUE_PULL = 0x1 << 6,
  PAD_CTL_PUE_PUD = 0x1 << 6, PAD_CTL_100K_PD = 0x0 << 4, PAD_CTL_47K_PU = 0x1 << 4, PAD_CTL_100K_PU = 0x2 << 4,
  PAD_CTL_22K_PU = 0x3 << 4, PAD_CTL_ODE_CMOS = 0x0 << 3, PAD_CTL_ODE_OpenDrain = 0x1 << 3, PAD_CTL_DRV_NORMAL = 0x0 << 1,
  PAD_CTL_DRV_HIGH = 0x1 << 1, PAD_CTL_DRV_MAX = 0x2 << 1, PAD_CTL_SRE_SLOW = 0x0 << 0, PAD_CTL_SRE_FAST = 0x1 << 0,
  PAD_CTL_NOLOOPBACK = 0x0 << 9, PAD_CTL_LOOPBACK = 0x1 << 9, PAD_CTL_PKE_NONE = 0x0 << 8, PAD_CTL_PKE_ENABLE = 0x1 << 8,
  PAD_CTL_PUE_KEEPER = 0x0 << 7, PAD_CTL_PUE_PUD = 0x1 << 7, PAD_CTL_100K_PD = 0x0 << 5, PAD_CTL_100K_PU = 0x1 << 5,
  PAD_CTL_47K_PU = 0x2 << 5, PAD_CTL_22K_PU = 0x3 << 5, PAD_CTL_HYS_CMOS = 0x0 << 4, PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
  PAD_CTL_ODE_CMOS = 0x0 << 3, PAD_CTL_ODE_OpenDrain = 0x1 << 3, PAD_CTL_DRV_NORMAL = 0x0 << 1, PAD_CTL_DRV_HIGH = 0x1 << 1,
  PAD_CTL_DRV_MAX = 0x2 << 1, PAD_CTL_SRE_SLOW = 0x0 << 0, PAD_CTL_SRE_FAST = 0x1 << 0, PAD_CTL_DRV_3_3V = 0x0 << 13,
  PAD_CTL_DRV_1_8V = 0x1 << 13, PAD_CTL_HYS_CMOS = 0x0 << 8, PAD_CTL_HYS_SCHMITZ = 0x1 << 8, PAD_CTL_PKE_NONE = 0x0 << 7,
  PAD_CTL_PKE_ENABLE = 0x1 << 7, PAD_CTL_PUE_KEEPER = 0x0 << 6, PAD_CTL_PUE_PUD = 0x1 << 6, PAD_CTL_100K_PD = 0x0 << 4,
  PAD_CTL_47K_PU = 0x1 << 4, PAD_CTL_100K_PU = 0x2 << 4, PAD_CTL_22K_PU = 0x3 << 4, PAD_CTL_ODE_CMOS = 0x0 << 3,
  PAD_CTL_ODE_OpenDrain = 0x1 << 3, PAD_CTL_DRV_NORMAL = 0x0 << 1, PAD_CTL_DRV_HIGH = 0x1 << 1, PAD_CTL_DRV_MAX = 0x2 << 1,
  PAD_CTL_SRE_SLOW = 0x0 << 0, PAD_CTL_SRE_FAST = 0x1 << 0, PAD_CTL_SRE_SLOW = 0x0 << 0, PAD_CTL_SRE_FAST = 0x1 << 0,
  PAD_CTL_DRV_LOW = 0x0 << 1, PAD_CTL_DRV_MEDIUM = 0x1 << 1, PAD_CTL_DRV_HIGH = 0x2 << 1, PAD_CTL_DRV_MAX = 0x3 << 1,
  PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, PAD_CTL_100K_PD = 0x0 << 4, PAD_CTL_47K_PU = 0x1 << 4,
  PAD_CTL_100K_PU = 0x2 << 4, PAD_CTL_22K_PU = 0x3 << 4, PAD_CTL_PUE_KEEPER = 0x0 << 6, PAD_CTL_PUE_PULL = 0x1 << 6,
  PAD_CTL_PKE_NONE = 0x0 << 7, PAD_CTL_PKE_ENABLE = 0x1 << 7, PAD_CTL_HYS_NONE = 0x0 << 8, PAD_CTL_HYS_ENABLE = 0x1 << 8,
  PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, PAD_CTL_DRV_VOT_LOW = 0x0 << 13, PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
  PAD_CTL_SRE_SLOW = 0x0 << 0, PAD_CTL_SRE_FAST = 0x1 << 0, PAD_CTL_DRV_LOW = 0x0 << 1, PAD_CTL_DRV_MEDIUM = 0x1 << 1,
  PAD_CTL_DRV_HIGH = 0x2 << 1, PAD_CTL_DRV_MAX = 0x3 << 1, PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
  PAD_CTL_100K_PD = 0x0 << 4, PAD_CTL_47K_PU = 0x1 << 4, PAD_CTL_100K_PU = 0x2 << 4, PAD_CTL_22K_PU = 0x3 << 4,
  PAD_CTL_PUE_KEEPER = 0x0 << 6, PAD_CTL_PUE_PULL = 0x1 << 6, PAD_CTL_PKE_NONE = 0x0 << 7, PAD_CTL_PKE_ENABLE = 0x1 << 7,
  PAD_CTL_HYS_NONE = 0x0 << 8, PAD_CTL_HYS_ENABLE = 0x1 << 8, PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
  PAD_CTL_DRV_VOT_LOW = 0x0 << 13, PAD_CTL_DRV_VOT_HIGH = 0x1 << 13
}
enum  iomux_pin_config {
  MUX_CONFIG_FUNC = 0, MUX_CONFIG_ALT1, MUX_CONFIG_ALT2, MUX_CONFIG_ALT3,
  MUX_CONFIG_ALT4, MUX_CONFIG_ALT5, MUX_CONFIG_ALT6, MUX_CONFIG_ALT7,
  MUX_CONFIG_SION = 0x1 << 4, MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, MUX_CONFIG_FUNC = 0, MUX_CONFIG_ALT1,
  MUX_CONFIG_ALT2, MUX_CONFIG_ALT3, MUX_CONFIG_ALT4, MUX_CONFIG_ALT5,
  MUX_CONFIG_ALT6, MUX_CONFIG_ALT7, MUX_CONFIG_SION = 0x1 << 4, MUX_CONFIG_GPIO = MUX_CONFIG_ALT5
}

Functions

void mxc_free_iomux (iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
void mxc_iomux_set_gpr (iomux_gp_func_t gp, bool en)
void mxc_iomux_set_input (iomux_input_select_t input, u32 config)
void mxc_iomux_set_pad (iomux_pin_name_t pin, u32 config)
int mxc_request_iomux (iomux_pin_name_t pin, iomux_pin_cfg_t cfg)


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