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Sourcecode: linux-fsl-imx51 version File versions  Download package

IOMUX SELECT_INPUT register index Base register is IOMUXSW_INPUT_CTL in iomux.c

Definition at line 87 of file iomux.h.

                                {
      MUX_IN_AUDMUX_P4_INPUT_DA_AMX = 0,
      MUX_IN_AUDMUX_P4_INPUT_DB_AMX,
      MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX,
      MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX,
      MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX,
      MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX,
      MUX_IN_AUDMUX_P7_INPUT_DA_AMX,
      MUX_IN_AUDMUX_P7_INPUT_TXFS_AMX,
      MUX_IN_CAN1_IPP_IND_CANRX,
      MUX_IN_CAN2_IPP_IND_CANRX,
      MUX_IN_CSI_IPP_CSI_D_0,
      MUX_IN_CSI_IPP_CSI_D_1,
      MUX_IN_CSPI1_IPP_IND_SS3_B,
      MUX_IN_CSPI2_IPP_CSPI_CLK_IN,
      MUX_IN_CSPI2_IPP_IND_DATAREADY_B,
      MUX_IN_CSPI2_IPP_IND_MISO,
      MUX_IN_CSPI2_IPP_IND_MOSI,
      MUX_IN_CSPI2_IPP_IND_SS0_B,
      MUX_IN_CSPI2_IPP_IND_SS1_B,
      MUX_IN_CSPI3_IPP_CSPI_CLK_IN,
      MUX_IN_CSPI3_IPP_IND_DATAREADY_B,
      MUX_IN_CSPI3_IPP_IND_MISO,
      MUX_IN_CSPI3_IPP_IND_MOSI,
      MUX_IN_CSPI3_IPP_IND_SS0_B,
      MUX_IN_CSPI3_IPP_IND_SS1_B,
      MUX_IN_CSPI3_IPP_IND_SS2_B,
      MUX_IN_CSPI3_IPP_IND_SS3_B,
      MUX_IN_ESDHC1_IPP_DAT4_IN,
      MUX_IN_ESDHC1_IPP_DAT5_IN,
      MUX_IN_ESDHC1_IPP_DAT6_IN,
      MUX_IN_ESDHC1_IPP_DAT7_IN,
      MUX_IN_ESDHC2_IPP_CARD_CLK_IN,
      MUX_IN_ESDHC2_IPP_CMD_IN,
      MUX_IN_ESDHC2_IPP_DAT0_IN,
      MUX_IN_ESDHC2_IPP_DAT1_IN,
      MUX_IN_ESDHC2_IPP_DAT2_IN,
      MUX_IN_ESDHC2_IPP_DAT3_IN,
      MUX_IN_ESDHC2_IPP_DAT4_IN,
      MUX_IN_ESDHC2_IPP_DAT5_IN,
      MUX_IN_ESDHC2_IPP_DAT6_IN,
      MUX_IN_ESDHC2_IPP_DAT7_IN,
      MUX_IN_FEC_FEC_COL,
      MUX_IN_FEC_FEC_CRS,
      MUX_IN_FEC_FEC_RDATA_2,
      MUX_IN_FEC_FEC_RDATA_3,
      MUX_IN_FEC_FEC_RX_CLK,
      MUX_IN_FEC_FEC_RX_ER,
      MUX_IN_I2C2_IPP_SCL_IN,
      MUX_IN_I2C2_IPP_SDA_IN,
      MUX_IN_I2C3_IPP_SCL_IN,
      MUX_IN_I2C3_IPP_SDA_IN,
      MUX_IN_KPP_IPP_IND_COL_4,
      MUX_IN_KPP_IPP_IND_COL_5,
      MUX_IN_KPP_IPP_IND_COL_6,
      MUX_IN_KPP_IPP_IND_COL_7,
      MUX_IN_KPP_IPP_IND_ROW_4,
      MUX_IN_KPP_IPP_IND_ROW_5,
      MUX_IN_KPP_IPP_IND_ROW_6,
      MUX_IN_KPP_IPP_IND_ROW_7,
      MUX_IN_SIM1_PIN_SIM_RCVD1_IN,
      MUX_IN_SIM1_PIN_SIM_SIMPD1,
      MUX_IN_SIM1_SIM_RCVD1_IO,
      MUX_IN_SIM2_PIN_SIM_RCVD1_IN,
      MUX_IN_SIM2_PIN_SIM_SIMPD1,
      MUX_IN_SIM2_SIM_RCVD1_IO,
      MUX_IN_UART3_IPP_UART_RTS_B,
      MUX_IN_UART3_IPP_UART_RXD_MUX,
      MUX_IN_UART4_IPP_UART_RTS_B,
      MUX_IN_UART4_IPP_UART_RXD_MUX,
      MUX_IN_UART5_IPP_UART_RTS_B,
      MUX_IN_UART5_IPP_UART_RXD_MUX,
      MUX_IN_USB_TOP_IPP_IND_OTG_USB_OC,
      MUX_IN_USB_TOP_IPP_IND_UH2_USB_OC,
} iomux_input_select_t;


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