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ssi_types.h

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/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 */

/*
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

 /*!
  * @file ssi_types.h
  * @brief This header file contains SSI types.
  *
  * @ingroup SSI
  */

#ifndef __MXC_SSI_TYPES_H__
#define __MXC_SSI_TYPES_H__

/*!
 * This enumeration describes the FIFO number.
 */
00027 typedef enum {
      /*!
       * FIFO 0
       */
00031       ssi_fifo_0 = 0,
      /*!
       * FIFO 1
       */
00035       ssi_fifo_1 = 1
} fifo_nb;

/*!
 * This enumeration describes the clock idle state.
 */
00041 typedef enum {
      /*!
       * Clock idle state is 1
       */
00045       clock_idle_state_1 = 0,
      /*!
       * Clock idle state is 0
       */
00049       clock_idle_state_0 = 1
} idle_state;

/*!
 * This enumeration describes I2S mode.
 */
00055 typedef enum {
      /*!
       * Normal mode
       */
00059       i2s_normal = 0,
      /*!
       * Master mode
       */
00063       i2s_master = 1,
      /*!
       * Slave mode
       */
00067       i2s_slave = 2
} mode_i2s;

/*!
 * This enumeration describes index for both SSI1 and SSI2 modules.
 */
00073 typedef enum {
      /*!
       * SSI1 index
       */
00077       SSI1 = 0,
      /*!
       * SSI2 index not present on MXC 91221 and MXC91311
       */
00081       SSI2 = 1
} ssi_mod;

/*!
 * This enumeration describes the status/enable bits for interrupt source of the SSI module.
 */
00087 typedef enum {
      /*!
       * SSI Transmit FIFO 0 empty bit
       */
00091       ssi_tx_fifo_0_empty = 0x00000001,
      /*!
       * SSI Transmit FIFO 1 empty bit
       */
00095       ssi_tx_fifo_1_empty = 0x00000002,
      /*!
       * SSI Receive FIFO 0 full bit
       */
00099       ssi_rx_fifo_0_full = 0x00000004,
      /*!
       * SSI Receive FIFO 1 full bit
       */
00103       ssi_rx_fifo_1_full = 0x00000008,
      /*!
       * SSI Receive Last Time Slot bit
       */
00107       ssi_rls = 0x00000010,
      /*!
       * SSI Transmit Last Time Slot bit
       */
00111       ssi_tls = 0x00000020,
      /*!
       * SSI Receive Frame Sync bit
       */
00115       ssi_rfs = 0x00000040,
      /*!
       * SSI Transmit Frame Sync bit
       */
00119       ssi_tfs = 0x00000080,
      /*!
       * SSI Transmitter underrun 0 bit
       */
00123       ssi_transmitter_underrun_0 = 0x00000100,
      /*!
       * SSI Transmitter underrun 1 bit
       */
00127       ssi_transmitter_underrun_1 = 0x00000200,
      /*!
       * SSI Receiver overrun 0 bit
       */
00131       ssi_receiver_overrun_0 = 0x00000400,
      /*!
       * SSI Receiver overrun 1 bit
       */
00135       ssi_receiver_overrun_1 = 0x00000800,
      /*!
       * SSI Transmit Data register empty 0 bit
       */
00139       ssi_tx_data_reg_empty_0 = 0x00001000,
      /*!
       * SSI Transmit Data register empty 1 bit
       */
00143       ssi_tx_data_reg_empty_1 = 0x00002000,

      /*!
       * SSI Receive Data Ready 0 bit
       */
00148       ssi_rx_data_ready_0 = 0x00004000,
      /*!
       * SSI Receive Data Ready 1 bit
       */
00152       ssi_rx_data_ready_1 = 0x00008000,
      /*!
       * SSI Receive tag updated bit
       */
00156       ssi_rx_tag_updated = 0x00010000,
      /*!
       * SSI Command data register updated bit
       */
00160       ssi_cmd_data_reg_updated = 0x00020000,
      /*!
       * SSI Command address register updated bit
       */
00164       ssi_cmd_address_reg_updated = 0x00040000,
      /*!
       * SSI Transmit interrupt enable bit
       */
00168       ssi_tx_interrupt_enable = 0x00080000,
      /*!
       * SSI Transmit DMA enable bit
       */
00172       ssi_tx_dma_interrupt_enable = 0x00100000,
      /*!
       * SSI Receive interrupt enable bit
       */
00176       ssi_rx_interrupt_enable = 0x00200000,
      /*!
       * SSI Receive DMA enable bit
       */
00180       ssi_rx_dma_interrupt_enable = 0x00400000,
      /*!
       * SSI Tx frame complete enable bit on MXC91221 & MXC91311 only
       */
00184       ssi_tx_frame_complete = 0x00800000,
      /*!
       * SSI Rx frame complete on MXC91221 & MXC91311 only
       */
00188       ssi_rx_frame_complete = 0x001000000
} ssi_status_enable_mask;

/*!
 * This enumeration describes the clock edge to clock in or clock out data.
 */
00194 typedef enum {
      /*!
       * Clock on rising edge
       */
00198       ssi_clock_on_rising_edge = 0,
      /*!
       * Clock on falling edge
       */
00202       ssi_clock_on_falling_edge = 1
} ssi_tx_rx_clock_polarity;

/*!
 * This enumeration describes the clock direction.
 */
00208 typedef enum {
      /*!
       * Clock is external
       */
00212       ssi_tx_rx_externally = 0,
      /*!
       * Clock is generated internally
       */
00216       ssi_tx_rx_internally = 1
} ssi_tx_rx_direction;

/*!
 * This enumeration describes the early frame sync behavior.
 */
00222 typedef enum {
      /*!
       * Frame Sync starts on the first data bit
       */
00226       ssi_frame_sync_first_bit = 0,
      /*!
       * Frame Sync starts one bit before the first data bit
       */
00230       ssi_frame_sync_one_bit_before = 1
} ssi_tx_rx_early_frame_sync;

/*!
 * This enumeration describes the Frame Sync active value.
 */
00236 typedef enum {
      /*!
       * Frame Sync is active when high
       */
00240       ssi_frame_sync_active_high = 0,
      /*!
       * Frame Sync is active when low
       */
00244       ssi_frame_sync_active_low = 1
} ssi_tx_rx_frame_sync_active;

/*!
 * This enumeration describes the Frame Sync active length.
 */
00250 typedef enum {
      /*!
       * Frame Sync is active when high
       */
00254       ssi_frame_sync_one_word = 0,
      /*!
       * Frame Sync is active when low
       */
00258       ssi_frame_sync_one_bit = 1
} ssi_tx_rx_frame_sync_length;

/*!
 * This enumeration describes the Tx/Rx frame shift direction.
 */
00264 typedef enum {
      /*!
       * MSB first
       */
00268       ssi_msb_first = 0,
      /*!
       * LSB first
       */
00272       ssi_lsb_first = 1
} ssi_tx_rx_shift_direction;

/*!
 * This enumeration describes the wait state number.
 */
00278 typedef enum {
      /*!
       * 0 wait state
       */
00282       ssi_waitstates0 = 0x0,
      /*!
       * 1 wait state
       */
00286       ssi_waitstates1 = 0x1,
      /*!
       * 2 wait states
       */
00290       ssi_waitstates2 = 0x2,
      /*!
       * 3 wait states
       */
00294       ssi_waitstates3 = 0x3
} ssi_wait_states;

/*!
 * This enumeration describes the word length.
 */
00300 typedef enum {
      /*!
       * 2 bits long
       */
00304       ssi_2_bits = 0x0,
      /*!
       * 4 bits long
       */
00308       ssi_4_bits = 0x1,
      /*!
       * 6 bits long
       */
00312       ssi_6_bits = 0x2,
      /*!
       * 8 bits long
       */
00316       ssi_8_bits = 0x3,
      /*!
       * 10 bits long
       */
00320       ssi_10_bits = 0x4,
      /*!
       * 12 bits long
       */
00324       ssi_12_bits = 0x5,
      /*!
       * 14 bits long
       */
00328       ssi_14_bits = 0x6,
      /*!
       * 16 bits long
       */
00332       ssi_16_bits = 0x7,
      /*!
       * 18 bits long
       */
00336       ssi_18_bits = 0x8,
      /*!
       * 20 bits long
       */
00340       ssi_20_bits = 0x9,
      /*!
       * 22 bits long
       */
00344       ssi_22_bits = 0xA,
      /*!
       * 24 bits long
       */
00348       ssi_24_bits = 0xB,
      /*!
       * 26 bits long
       */
00352       ssi_26_bits = 0xC,
      /*!
       * 28 bits long
       */
00356       ssi_28_bits = 0xD,
      /*!
       * 30 bits long
       */
00360       ssi_30_bits = 0xE,
      /*!
       * 32 bits long
       */
00364       ssi_32_bits = 0xF
} ssi_word_length;

#endif                        /* __MXC_SSI_TYPES_H__ */

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