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mxc_scc2_driver.h File Reference


Detailed Description

(Header file to use the SCC2 driver.)

The SCC2 driver is available to other kernel modules directly. Secure Partition functionality is extended to users through the SHW API. Other functionality of the SCC2 is limited to kernel-space users.

With the exception of scc_monitor_security_failure(), all routines are 'synchronous', i.e. they will not return to their caller until the requested action is complete, or fails to complete. Some of these functions could take quite a while to perform, depending upon the request.

Routines are provided to:

The SCC2 encrypts and decrypts using Triple DES with an internally stored key. When the SCC2 is in Secure mode, it uses its secret, unique-per-chip key. When it is in Non-Secure mode, it uses a default key. This ensures that secrets stay secret if the SCC2 is not in Secure mode.

Not all functions that could be provided in a 'high level' manner have been implemented. Among the missing are interfaces to the ASC/AIC components and the timer functions. These and other features must be accessed through scc_read_register() and scc_write_register(), using the #define values provided.

Here is a glossary of acronyms used in the SCC2 driver documentation:

Definition in file mxc_scc2_driver.h.

Go to the source code of this file.

Classes

struct  scc_config_t

Defines

#define INT_SCC_SCM   MXC_INT_SCC_SCM
#define INT_SCC_SMN   MXC_INT_SCC_SMN
#define SCC_ADDRESS_RANGE   (SMN_ADDR_OFFSET + SMN_REG_BANK_SIZE)
#define SCC_DRIVER_MAJOR_VERSION   2
#define SCC_DRIVER_MINOR_VERSION_0   0
#define SCC_DRIVER_MINOR_VERSION_2   2
#define SCM_ACC0_REG   0x084
#define SCM_ACC10_REG   0x0d4
#define SCM_ACC11_REG   0x0dc
#define SCM_ACC12_REG   0x0e4
#define SCM_ACC13_REG   0x0ec
#define SCM_ACC14_REG   0x0f4
#define SCM_ACC15_REG   0x0fc
#define SCM_ACC1_REG   0x08c
#define SCM_ACC2_REG   0x094
#define SCM_ACC3_REG   0x09c
#define SCM_ACC4_REG   0x0a4
#define SCM_ACC5_REG   0x0ac
#define SCM_ACC6_REG   0x0b4
#define SCM_ACC7_REG   0x0bc
#define SCM_ACC8_REG   0x0c4
#define SCM_ACC9_REG   0x0cc
#define SCM_AES_CBC_IV0_REG   0x060
#define SCM_AES_CBC_IV1_REG   0x064
#define SCM_AES_CBC_IV2_REG   0x068
#define SCM_AES_CBC_IV3_REG   0x06c
#define SCM_C_BLACK_ST_REG   0x058
#define SCM_CBC_MODE   0x2
#define SCM_CCMD_AES   1
#define SCM_CCMD_AES_DEC_CBC   5
#define SCM_CCMD_AES_DEC_ECB   1
#define SCM_CCMD_AES_ENC_CBC   7
#define SCM_CCMD_AES_ENC_ECB   3
#define SCM_CCMD_CBC   4
#define SCM_CCMD_CCMD_MASK   0x0000000F
#define SCM_CCMD_CCMD_SHIFT   0
#define SCM_CCMD_DEC   0
#define SCM_CCMD_ECB   0
#define SCM_CCMD_ENC   2
#define SCM_CCMD_LENGTH_MASK   0xFFF00000
#define SCM_CCMD_LENGTH_SHIFT   20
#define SCM_CCMD_OFFSET_MASK   0x000FFF00
#define SCM_CCMD_OFFSET_SHIFT   8
#define SCM_CCMD_PART_MASK   0x000000F0
#define SCM_CCMD_PART_SHIFT   4
#define SCM_CCMD_REG   0x054
#define SCM_DBG_STATUS_REG   0x05c
#define SCM_DECRYPT_MODE   0x1
#define SCM_ECB_MODE   0x0
#define SCM_ENCRYPT_MODE   0x0
#define SCM_ERCD_BLK_OVFL   0x6
#define SCM_ERCD_CPHR_OVFL   0x9
#define SCM_ERCD_DEVICE_BUSY   0xC
#define SCM_ERCD_DMA_ERROR   0x5
#define SCM_ERCD_NO_KEY   0x7
#define SCM_ERCD_PROC_INTR   0xA
#define SCM_ERCD_READ_PERM   0x3
#define SCM_ERCD_UNALGN_ADDR   0xD
#define SCM_ERCD_UNK_ADDR   0x1
#define SCM_ERCD_UNK_CMD   0x2
#define SCM_ERCD_WRITE_PERM   0x4
#define SCM_ERCD_WRNG_KEY   0xB
#define SCM_ERCD_ZRZ_OVFL   0x8
#define SCM_ERR_STATUS_REG   0x010
#define SCM_ERRSTAT_ERC_MASK   0x00000F00
#define SCM_ERRSTAT_ERC_SHIFT   8
#define SCM_ERRSTAT_ILM   0x00080000
#define SCM_ERRSTAT_MID_MASK   0x00F00000
#define SCM_ERRSTAT_MID_SHIFT   20
#define SCM_ERRSTAT_SMS_MASK   0x000000F0
#define SCM_ERRSTAT_SMS_SHIFT   4
#define SCM_ERRSTAT_SRS_MASK   0x0000000F
#define SCM_ERRSTAT_SRS_SHIFT   0
#define SCM_ERRSTAT_SUP   0x00008000
#define SCM_FAULT_ADR_REG   0x014
#define SCM_INT_CTL_REG   0x008
#define SCM_MAJOR_VERSION_2   2
#define SCM_PART_ENGAGED_REG   0x01c
#define SCM_PART_OWNERS_REG   0x018
#define SCM_PENG_ENGAGED   1
#define SCM_PENG_SHIFT   1
#define SCM_PERM_HD_EXECUTE   0x00000100
#define SCM_PERM_HD_READ   0x00000400
#define SCM_PERM_HD_SUP_DISABLE   0x00000800
#define SCM_PERM_HD_WRITE   0x00000200
#define SCM_PERM_MASK   0xC0000F67
#define SCM_PERM_NO_ZEROIZE   0x10000000
#define SCM_PERM_OT_EXECUTE   0x00000001
#define SCM_PERM_OT_READ   0x00000004
#define SCM_PERM_OT_WRITE   0x00000002
#define SCM_PERM_TH_READ   0x00000040
#define SCM_PERM_TH_WRITE   0x00000020
#define SCM_POWN_MASK   3
#define SCM_POWN_PART_FREE   0
#define SCM_POWN_PART_OTHER   2
#define SCM_POWN_PART_OWNED   3
#define SCM_POWN_PART_UNUSABLE   1
#define SCM_POWN_SHIFT   2
#define SCM_REG_BANK_SIZE   0x100
#define SCM_REG_BANK_SIZE   0x100
#define SCM_SMID0_REG   0x080
#define SCM_SMID10_REG   0x0d0
#define SCM_SMID11_REG   0x0d8
#define SCM_SMID12_REG   0x0e0
#define SCM_SMID13_REG   0x0e8
#define SCM_SMID14_REG   0x0f0
#define SCM_SMID15_REG   0x0f8
#define SCM_SMID1_REG   0x088
#define SCM_SMID2_REG   0x090
#define SCM_SMID3_REG   0x098
#define SCM_SMID4_REG   0x0a0
#define SCM_SMID5_REG   0x0a8
#define SCM_SMID6_REG   0x0b0
#define SCM_SMID7_REG   0x0b8
#define SCM_SMID8_REG   0x0c0
#define SCM_SMID9_REG   0x0c8
#define SCM_SMID_WIDTH   8
#define SCM_STATUS_BAR   0x00000010
#define SCM_STATUS_BIG   0x00000040
#define SCM_STATUS_ERR   0x00008000
#define SCM_STATUS_KST_BAD_KEY   0x10000000
#define SCM_STATUS_KST_DEFAULT_KEY   0x80000000
#define SCM_STATUS_KST_RESERVED1   0x40000000
#define SCM_STATUS_KST_WRONG_KEY   0x20000000
#define SCM_STATUS_MSS_FAIL   0x00004000
#define SCM_STATUS_MSS_SEC   0x00002000
#define SCM_STATUS_REG   0x00c
#define SCM_STATUS_RSS_FAIL   0x00000400
#define SCM_STATUS_RSS_INIT   0x00000100
#define SCM_STATUS_RSS_SEC   0x00000200
#define SCM_STATUS_SRS_ABUSY   0x4
#define SCM_STATUS_SRS_ADONE   0xD
#define SCM_STATUS_SRS_CBUSY   0x3
#define SCM_STATUS_SRS_CDONE   0x6
#define SCM_STATUS_SRS_CDONE2   0x8
#define SCM_STATUS_SRS_FAIL   0xF
#define SCM_STATUS_SRS_MASK   0x0000000F
#define SCM_STATUS_SRS_READY   0x1
#define SCM_STATUS_SRS_RESET   0x0
#define SCM_STATUS_SRS_SHIFT   0
#define SCM_STATUS_SRS_ZBUSY   0x2
#define SCM_STATUS_SRS_ZDONE   0x5
#define SCM_STATUS_SRS_ZDONE2   0x7
#define SCM_STATUS_UNV   0x00000080
#define SCM_STATUS_USK   0x00000020
#define SCM_UNIQUE_ID0_REG   0x020
#define SCM_UNIQUE_ID1_REG   0x024
#define SCM_UNIQUE_ID2_REG   0x028
#define SCM_UNIQUE_ID3_REG   0x02c
#define SCM_VER_BPCB_MASK   0x001F0000
#define SCM_VER_BPCB_SHIFT   16
#define SCM_VER_BPP_MASK   0xFF000000
#define SCM_VER_BPP_SHIFT   24
#define SCM_VER_MAJ_MASK   0x00000F00
#define SCM_VER_MAJ_SHIFT   8
#define SCM_VER_MIN_MASK   0x000000FF
#define SCM_VER_MIN_SHIFT   0
#define SCM_VER_NP_MASK   0x0000F000
#define SCM_VER_NP_SHIFT   12
#define SCM_VERSION_REG   0x000
#define SCM_ZCMD_CCMD_MASK   0x0000000F
#define SCM_ZCMD_CCMD_SHIFT   0
#define SCM_ZCMD_PART_MASK   0x000000F0
#define SCM_ZCMD_PART_SHIFT   4
#define SCM_ZCMD_REG   0x050
#define SMN_ADDR_OFFSET   0x100
#define SMN_BB_CNT_REG   (SMN_ADDR_OFFSET+0x00000014)
#define SMN_BB_DEC_REG   (SMN_ADDR_OFFSET+0x0000001c)
#define SMN_BB_INC_REG   (SMN_ADDR_OFFSET+0x00000018)
#define SMN_BIT_COUNT_MASK   0x000007ff
#define SMN_BITBANK_DECREMENT_MASK   0x000007ff
#define SMN_BITBANK_INC_SIZE_MASK   0x000007ff
#define SMN_COMMAND_CLEAR_BIT_BANK   0x4
#define SMN_COMMAND_CLEAR_INTERRUPT   0x8
#define SMN_COMMAND_ENABLE_INTERRUPT   0x2
#define SMN_COMMAND_REG   (SMN_ADDR_OFFSET+0x00000004)
#define SMN_COMMAND_SET_SOFTWARE_ALARM   0x1
#define SMN_COMMAND_ZEROS_MASK   0xfffffff0
#define SMN_COMPARE_REG   (SMN_ADDR_OFFSET+0x00000020)
#define SMN_COMPARE_SIZE_MASK   0x0000003f
#define SMN_CT_CHK_REG   (SMN_ADDR_OFFSET+0x00000028)
#define SMN_DBG_D1   0x0001
#define SMN_DBG_D10   0x0200
#define SMN_DBG_D11   0x0400
#define SMN_DBG_D12   0x0800
#define SMN_DBG_D2   0x0002
#define SMN_DBG_D3   0x0004
#define SMN_DBG_D4   0x0008
#define SMN_DBG_D5   0x0010
#define SMN_DBG_D6   0x0020
#define SMN_DBG_D7   0x0040
#define SMN_DBG_D8   0x0080
#define SMN_DBG_D9   0x0100
#define SMN_DBG_ZEROS_MASK   0xfffff000
#define SMN_HAC_REG   (SMN_ADDR_OFFSET+0x0000003c)
#define SMN_PT_CHK_REG   (SMN_ADDR_OFFSET+0x00000024)
#define SMN_REG_BANK_SIZE   0x40
#define SMN_SEC_VIO_REG   (SMN_ADDR_OFFSET+0x00000034)
#define SMN_SEQ_CHECK_REG   (SMN_ADDR_OFFSET+0x00000010)
#define SMN_SEQ_END_REG   (SMN_ADDR_OFFSET+0x0000000c)
#define SMN_SEQ_START_REG   (SMN_ADDR_OFFSET+0x00000008)
#define SMN_SEQUENCE_CHECK_MASK   0x0000ffff
#define SMN_SEQUENCE_END_MASK   0x0000ffff
#define SMN_SEQUENCE_START_MASK   0x0000ffff
#define SMN_STATE_FAIL   0x9
#define SMN_STATE_HEALTH_CHECK   0x6
#define SMN_STATE_NON_SECURE   0xC
#define SMN_STATE_SECURE   0xA
#define SMN_STATE_START   0x0
#define SMN_STATE_ZEROIZE_RAM   0x5
#define SMN_STATUS_ASC_ERROR   0x00000200
#define SMN_STATUS_BITBANK_ERROR   0x00000400
#define SMN_STATUS_ILLEGAL_MASTER   0x01000000
#define SMN_STATUS_INTERNAL_BOOT   0x00000020
#define SMN_STATUS_PC_ERROR   0x00000800
#define SMN_STATUS_PERIP_INIT   0x00010000
#define SMN_STATUS_REG   (SMN_ADDR_OFFSET+0x00000000)
#define SMN_STATUS_SCAN_EXIT   0x00800000
#define SMN_STATUS_SEC_VIO_ACTIVE_ERROR   0x00000080
#define SMN_STATUS_SECURITY_POLICY_ERROR   0x00000100
#define SMN_STATUS_SMN_ERROR   0x00004000
#define SMN_STATUS_SMN_STATUS_IRQ   0x00004000
#define SMN_STATUS_SOFTWARE_ALARM   0x00002000
#define SMN_STATUS_STATE_MASK   0x0000001F
#define SMN_STATUS_STATE_SHIFT   0
#define SMN_STATUS_TIMER_ERROR   0x00001000
#define SMN_STATUS_VERSION_ID_MASK   0xfc000000
#define SMN_STATUS_VERSION_ID_SHIFT   28
#define SMN_TIMER_CTL_REG   (SMN_ADDR_OFFSET+0x00000030)
#define SMN_TIMER_CTRL_ZEROS_MASK   0xfffffffc
#define SMN_TIMER_IV_REG   (SMN_ADDR_OFFSET+0x0000002c)
#define SMN_TIMER_LOAD_TIMER   0x2
#define SMN_TIMER_REG   (SMN_ADDR_OFFSET+0x00000038)
#define SMN_TIMER_START_TIMER   0x1
#define SMN_TIMER_STOP_MASK   0x1
#define Z_INT_EN   0x00000002
#define ZCMD_DEALLOC_PART   3

Enumerations

enum  scc_cypher_mode_t { SCC_CYPHER_MODE_ECB = 1, SCC_CYPHER_MODE_CBC = 2 }
enum  scc_enc_dec_t { SCC_ENCRYPT, SCC_DECRYPT, SCC_ENCRYPT, SCC_DECRYPT }
enum  scc_partition_status_t {
  SCC_PART_S_UNUSABLE, SCC_PART_S_UNAVAILABLE, SCC_PART_S_AVAILABLE, SCC_PART_S_ALLOCATED,
  SCC_PART_S_ENGAGED
}
enum  scc_return_t {
  SCC_RET_OK = 0, SCC_RET_FAIL, SCC_RET_VERIFICATION_FAILED, SCC_RET_TOO_MANY_FUNCTIONS,
  SCC_RET_BUSY, SCC_RET_INSUFFICIENT_SPACE, SCC_RET_OK = 0, SCC_RET_FAIL,
  SCC_RET_VERIFICATION_FAILED, SCC_RET_TOO_MANY_FUNCTIONS, SCC_RET_BUSY, SCC_RET_INSUFFICIENT_SPACE
}
enum  scc_verify_t { SCC_VERIFY_MODE_NONE, SCC_VERIFY_MODE_CCITT_CRC, SCC_VERIFY_MODE_NONE, SCC_VERIFY_MODE_CCITT_CRC }

Functions

scc_return_t scc_allocate_partition (uint32_t smid_value, int *part_no, void **part_base, uint32_t *part_phys)
scc_return_t scc_decrypt_region (uint32_t part_base, uint32_t offset_bytes, uint32_t byte_count, uint8_t *black_data, uint32_t *IV, scc_cypher_mode_t cypher_mode)
scc_return_t scc_diminish_permissions (void *part_base, uint32_t permissions)
scc_return_t scc_encrypt_region (uint32_t part_base, uint32_t offset_bytes, uint32_t byte_count, uint8_t *black_data, uint32_t *IV, scc_cypher_mode_t cypher_mode)
scc_return_t scc_engage_partition (void *part_base, const uint8_t *UMID, uint32_t permissions)
scc_config_tscc_get_configuration (void)
scc_return_t scc_monitor_security_failure (void callback_func(void))
scc_partition_status_t scc_partition_status (void *part_base)
scc_return_t scc_read_register (int register_offset, uint32_t *value)
scc_return_t scc_release_partition (void *part_base)
void scc_set_sw_alarm (void)
void scc_stop_monitoring_security_failure (void callback_func(void))
uint32_t scc_virt_to_phys (void *address)
scc_return_t scc_write_register (int register_offset, uint32_t value)
scc_return_t scc_zeroize_memories (void)


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